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AS4SD16M72PBG-s/IT,ET,XT
16M x 72, SDR SDRAM MCP 25mm x 32mm, 219 PBGA 1.27mm Pitch
Revision 0.3 (May 31,06) -for new lower ICC limits
Development / ADVANCE Information
Product Information is subject to change or be canceled without notice!
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AS4SD16M72PBG-s/IT,ET,XT
16M x 72, SDR SDRAM, 3.3v Core/ 3.3v IO
Features
* * * * * * * * * * * * * Performance: 100MHz, 125MHz and 133MHz Core Supply Voltage = 3.3v +/- 0.3v IO Supply Voltage = 3.3v +/- 0.3v Internal, pipeline, architecture Single Clock Input Positive edge; Command execution DLL for alignment of DQ and DQS transitions Four internal banks for concurrent operation Data Mask (DM) for masking write data Programmable IOL/IOH Programmable Burst length: 1,2,4,8 or full page Auto Precharge Self Refresh Mode on /IT and /ET devices
This architecture is compatible with the 2n rule of PREFETCH architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. PRECHARGING one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless array access at rated speed.
Initialization
Austin Semiconductor's AS4SD16M72PBG is like all other SDRAM devices and for correct functional operation must be properly initialized in a predefined manor, following the allowable functional modes. Operation of the device outside of the prescribed modes may result in undefined device operation. Once power is applied to VDD and VDDQ and the clock is stable, the device requires a 100us delay prior to issuing a command other than a COMMAND INHIBIT or NOP. Starting at some point during this 100us period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands should be applied. Once the 100us delay has been satisfied with at least one COMMAND INHIBIT or NOP, a PRECHARGE command should be applied. All banks must then be PRECHARGED, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command.
Silicon Base:
*Micron: Die equivalency to MT48LC16M16A2
General Description
Austin Semiconductor's 1.2Gb, Synchronous DRAM is a high speed CMOS MCP and is packaged in a 25mm x 32mm, 219 PBGA with a ball pitch of 1.27mm. This device contains (5) x16 synchronous dynamic random access die, each containing a total density of 268,435,456 bits. The end organization of the MCP is 16M x 80. Read and Write accesses to the array are burst oriented; accesses start at a selected location and continue for a programmed number of locations, as prescribed by the programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered at the initiation of READ or WRITE are used to select the starting column location for the burst access. The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4, 8 or full page, with a burst terminate option. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. Austin Semiconductor's AS4SD16M72PBG device uses an internal pipeline architecture to achieve high speed operation.
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Register Definition [MODE REGISTER]
The mode register is used to define the specific mode of operation of the SDRAM MCP. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a WRITE burst mode. The MODE REGISTER is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode register bits M0-M2 specify the burst length, M3
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Specifies the type of burst (sequential or interleaved), M4-M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the WRITE BURST mode and M10, M11 are reserved for future use. Address A12 (M12) is undefined but should be driven LOW during loading of the MODE REGISTER. The MODE REGISTER must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation.
N + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, If a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will be valid by T2. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Operating Mode Burst Length
READ and WRITE accesses to the SDRAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1,2,4 and 8 locations are available for both the sequential and the interleaved burst types, and a full page burst is available for the sequential burst mode. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, aas unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst will wrap within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A2-A8 (each x16) when the burst length is set to four; and by A3-A8 (each x16) when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached. The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test Modes and reserved states should not be used because unknown operation or incompatibility with future version may result.
Write Burst Mode
When M9=0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9=1, the programmed burst length applies to READ bursts, but WRITE accesses are single-location (non-burst) accesses.
Command Inhibit
The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected.
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of first valid data presented on the Output bus (DQ0-DQ79). The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge
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No Operation (NOP)
The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS\ is LOW). This prevents unwanted commands from being registered during IDLE or WAIT states. Operations already in progress are not affected.
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Load Mode Register
The MODE REGISTER is loaded via inputs A0-A11 (A12 should be driven LOW). See MODE REGISTER heading in the REGISTER DEFINITION section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met.
HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location.
Precharge
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be PRECHARGED, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as "Don't Care". Once a bank has been PRECHARGED, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank.
Active
The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank.
Auto Precharge
AUTO PRECHARGE is a feature which performs the same individual bank PRECHARGE function described above, without requiring an explicit command. This is accomplished by using A10 to enable AUTO PRECHARGE in conjunction with a specific READ or WRITE command. A PRECHARGE of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the full-page burst mode, where AUTO PRECHARGE does not apply. AUTO PRECHARGE is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. AUTO PRECHARGE ensures that the PRECHARGE is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the PRECHARGE time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type Operation.
Read
The read command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A8 (each x16) selects the starting column location. The value on input A10 determines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row will remain open for subsequent accesses. READ data appears on the DQs subject to the logic level on the DQM inputs two clocks earlier. If a given DQM signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQM signal was registered LOW, the DQs will provide valid data.
Write
The WRITE command is used to initiate a BURST WRITE access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A8 (each x16) selects the starting column location. The value on input A10 determines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be PRECHARGED at the end of the WRITE BURST; if for subsequent accesses input data appearing on the DQs is WRITTEN to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is
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Burst Terminate
The BURST TERMINATE command is used to truncate either a fixed-length or full-page burst. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated.
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Auto Refresh
AUTO REFRESH is used during normal operation of the SDRAM MCP and is analogous to CAS\-BEFORE-RAS\ (CBR) REFRESH in conventional DRAMs. This command is non-persistent, so it must be issued each time a refresh is required. All active banks must be PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH command should not be issued until the minimum tRP has been met after the PRECHARGE command. The addressing is generated by the internal REFRESH controller. This makes the address bits "Don't Care" during an AUTO REFRESH command. The 256Mb SDRAM MCP requires 8,192 AUTO REFRESH cycles every 64ms (tREF). Providing a distributed AUTO REFRESH command every 7.81us will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 8,192 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate (tRFC), once every 64ms.
Upon exiting the SELF REFRESH mode, AUTO REFRESH commands must be issued every 7.81us or less as both SELF REFRESH and AUTO REFRESH utilize the row refresh counter.
Self Refresh
The SELF REFRESH command can be used to retain data in the SDRAM MCP, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM MCP retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the inputs to the SDRAM MCP become "Don't Care" with the exception of CKE, which must remain LOW. Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own AUTO REFRESH cycles. The SDRAM MCP must remain in SELF REFRESH mode for a minimum period equal to tRAS and may remain in SELF REFRESH for an indefinite period of time beyond the minimum. The procedure for exiting SELF REFRESH requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM MCP must have NOP commands issued (a minimum of two clocks) for tXSR because time is required for the completion of any internal REFRESH in progress.
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Block Diagram :
25mm x 32mm 219 BGA (1.27 mm pitch)
VCC VCCQ VSS CLK2 CLK1 CKE1 CS1\ WE1\ RAS1\ CAS1\ DQML1 DQMH1 SDR SDRAM X16
3.3v Core 3.3v IO
AD DR
BA 0 BA 1
SDR SDRAM X16
3.3v Core 3.3v IO
CKE2 CS2\ WE2\ RAS2\ CAS2\ DQML2 DQMH2
DQ32-47 CLK4 DQ16-31 CLK0 CLK0\ CKE0 CS0\ WE0\ RAS0\ CAS0\ DQML0 DQMH0 DQSL0 DQSH0 DQ0-15 SDR SDRAM X16
3.3v Core 3.3v IO
SDR SDRAM X16
3.3v Core 3.3v IO 3
CKE4 CS4\ WE4\ RAS4\ CAS4\ DQML4 DQMH4
DQ64-79 CLK3 SDR SDRAM X16
3.3v Core 3.3v IO
CKE3 CS3\ WE3\ RAS3\ CAS3\ DQML3 DQMH3
DQ48-63
Signal Layer(s)
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Ground Plane
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VDD
VDDQ
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SDRAM-SDR Pinout Top View Rev. A, 12/04 - X72/X80 1 2 3 4 a b c d e f g h j k l m n p r t
DQ1 DQ3 DQ6 DQ7 CAS0\ CS0\ VSS VSS NC NC DQ56 DQ57 DQ60 DQ62 VSS DQ0 DQ2 DQ4 DQ5 DQML0 WE0\ RAS0\ VSS VSS CKE3 CLK3 DQMH3 DQ58 DQ59 DQ61 DQ63 DQ14 DQ12 DQ10 DQ8 VCC VCC VCC VCC VCC VCC VCC VCC DQ55 DQ53 DQ51 DQ49 DQ15 DQ13 DQ11 DQ9 DQMH0 CLK0 CKE0 VCCQ VCCQ CS3\ CAS3\ WE3\ DQ54 DQ52 DQ50 DQ48
5
VSS VSS VCC VCCQ NC NC NC VSS VSS NC RAS3\ DQML3 NC VSS VCC VCCQ
6
VSS VSS VCC VCCQ NC
7
A9 A0 A2 A12 NC
8
A10 A7 A5 DNU BA0
9
A11 A6 A4 DNU BA1
10
A8 A1 A3 DNU NC
11
VCCQ VCC VSS VSS NC
12
VCCQ VCC VSS VSS NC RAS1\ CAS\ VCC VCC NC NC
13
DQ16 DQ18 DQ20 DQ22 DQML1 WE1\ CS1\ VSS VSS CKE2 CLK2 DQMH2 DQ41 DQ43 DQ45 DQ47
14
DQ17 DQ19 DQ21 DQ23 VSS VSS VSS VSS VSS VSS VSS VSS DQ40 DQ42 DQ44 DQ46
15
DQ31 DQ29 DQ27 DQ26 NC DQMH1 NC VCCQ VCCQ RAS2\ WE2\ DQML2 DQ37 DQ36 DQ34 DQ32
16
VSS DQ30 DQ28 DQ25 DQ24 CLK1 CKE1 VCC VCC CS2\
a b c d e f g h j k
CAS2\ l DQ39 DQ38 DQ35 DQ33 VCC
CKE4 NC VSS VCC VCCQ
DQMH4 DQ73 DQ75 DQ77 DQ79
CLK4 DQ72 DQ74 DQ76 DQ78
CAS4\ DQ71 DQ69 DQ67 DQ65
WE4\ DQ70 DQ68 DQ66 DQ64
RAS4\ DQML4 VCC VSS VSS
CS4\ NC VCC VSS VSS
m n p r t
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Ground
Array Power
D/Q Power
Address
Data IO
NC
CNTRL
ADDRESS/ DNU
UNPOPULATED
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Pin Descriptions
BGA Locations F4, F16, L2, L13, SYMBOL CKx DESCRIPTION
Clock: CKx is the clock input. All address and control input signals are sampled on the crossing of the positive edge of CKx\. Output data (DQ's and DQS) is referenced to rising edge of CLKx
G4, G16, K2, K13 M6
CKEx
Clock Enable: CKE controls the clock inputs. CKE high enables, CKE Low disables the clock input pins. Driving CKE Low provides PRECHARGE POWER-DOWN and SELF REFRESH operations, or ACT IVE POWER-DOWN. CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry CKE is Asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers are disabled during POWER-DOWN Input buffers are disabled during SELF REFRESH.
G1, G13, K4, K16 M12
CSx\
Chip Select: CSx\ enagles the COMMAND register(s) of each of the five (5) contained words. All commands are masked when CSx\ is registered HIGH. CSx\ provides for external bank selection on systems with multiple banks. CSx\ is considered part of the COMMAND CODE.
F4, F16, G5, G15, K1, K12, L2, L13, N7, M9 G4, G16, K2, K14 M7
RASx\, CASx\ WEx\
Command Inputs: RASx, CASx, and Wex\ define the command being entered
DQMLx, DQMHx Input Data Mask. DM is an input mask signal for write data.
Input data is masked when DQMLx or Hx is sampled HIGH at time of a WRIT E access. DM is sampled on both edges of DQSLx and DQSHx
E8, E9
BA0, BA1
Bank Address Inputs: BA0, BA1 define which bank an ACT IVE READ, WRIT E, or PRECHARGE command is being applied Address Input: Provide the row address for Active commands, and the column address and auto precharge bit (A10) for READ/WRIT E commands to select one location out of the memory array int the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank or all banks. T he address inputs also provide the op-code during a MODE RESIST ER SET command.
A7, A8, A9, A10, B7 A0-A11, A12 B8, B9, B10, C7, C8 C9, C10, D7
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Pin Descriptions
BGA Locations SYMBOL A2, A3, A4, A13, A14 DQ0-79 B1, B2, B3, B4, B13 B14, B15, B16, C1, C2,C3,C4,C13,C14, C15,C16,D1,D2,D3, D4,D13,D14,D15,D16 E1,E16,M1,M16,N1 N2,N3,N4,N13,N14, N15,N16,P1,P2,P3, P4,P13,P14,P15,P16 R1,R2,R3,R4,R13, R14,R15,R16,T2,T3, T4,T13,T14,T15,N7, N8,N9,N10,P7,P8,P9 P10,R7,R8,R9,R10 T7,T8,T9,T10 B11,B12,C5,C6,E3, VCC F3,G3,H3,H12,H16, J3,J12,J16,K3,L3,M3 P11,P12,R5,R6,T16 A11,A12,D5,D6,H4, VCCQ H15,J4,J15,T5,T6 A5,A6,A16,B5,B6, VSS C11,C12,D11,D12, E14,F14,G14,H1,H2, H5,H13,H14,J1,J2,J5 J13,J14,K14,L14 P5,P6,R11,R12,T1, T11,T12, M14 E5,E6,E7,E10,E11, NC E12,E15,F5,G5,G15, K1,K5,K12,L12,N5, N6,N12 DESCRIPTION
Data I/O
Core Power Supply
I/O Power Supply Ground (Digital)
Not Connected Internally
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Mode Register Definition
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ADDRESS BUS
12
11
10
9
8
7
6
5
4
3
2
1
0
MODE REGISTER (Mx)
Unused Reserved
WB
Op Mode
CAS Latency
BT
Burst Length
Burst Length M6 0 0 0 0 1 1 1 1 M5 0 0 1 1 0 0 1 1 M4 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved M2 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 M3=0 1 2 4 8 Reserved Reserved Reserved Full Page M3=1 1 2 4 8 Reserved Reserved Reserved Reserved
M3 0 1
Burst Type Sequential Interleaved
M8 0 1
M7 0 0
M6 - M0 Valid Valid
Operating Mode Normal Operation Normal Operation / Reset DLL
M9 0 1
Operating Mode Normal Operation Single Location Access
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16M x 72, SDR SDRAM, 3.3v Core/ 3.3v IO Recommended IO Consideration(s) X72 Designs
DQ64 DQ65 DQ66 DQ67 DQ68 DQ69 DQ70 DQ71 DQ72 DQ73 DQ74 DQ75 DQ76 DQ77 DQ78 DQ79 TO SYSTEM IO
X80 Designs
DQ64 DQ65 DQ66 DQ67 DQ68 DQ69 DQ70 DQ71 DQ72 DQ73 DQ74 DQ75 DQ76 DQ77 DQ78 DQ79
TO SYSTEM IO
TO SYSTEM IO
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Mechanical :
1
23
4
5
67
8 9 10 11 12 13 14 15 16
T R P N M L K 19.05 NOM J H G F 1.27 NOM E D C B A
(Bottom View)
24.90 25.10
1.27 NOM 31.90 32.10
219 x O 0.762 NOM
0.61 NOM
2.03 MAX
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DC Electrical Characteristics and Operating Conditions
PARAMETER/CONDITION Supply Voltage I/O Supply Voltage Input High (Logic 1) Voltage Input Low (Logic 0) Voltage SYMBOL VDD VDDQ VIH(DC) VIL(DC) MIN 3.0 3.0 2.0 -0.3 MAX 3.6 3.6 VDD + 0.3 0.8 UNITS V V V V NOTES
INPUT LEAKAGE (non address) INPUT LEAKAGE (address) Any input 0V VIN VDD, VREF PIN 0V VIN 1.35V (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT (DQs are disabled; 0V VOUT VDDQ) OUTPUT LEVELS: High Current (VOUT = 2.4V
II II
-5 -25
5 25
A A
IOZ
-5
5
A
IOH
-4.0
-
mA
minimum VTT) Low Current (VOUT = 0.4V, IOL 4.0 mA
Capacitance
DESCRIPTIONS
Address; A0-A12, BA0, BA1 Input / Output TA = 25 C; f = 1Mhz Clocks; CLKx, CLKx\, CKEx Input Pins: all other input only Cck CI 8 9 pF pF
CONDITIONS
Sym
Ca CIO
Typ
30 12
UNITS
pF pF
NOTES
Note(s): Power calculated with Ouputs unloaded
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MAX PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst = 2, READ or WRITE, tRC = tRC MIN SYMBOL ICC1 -75 625 -8 600 -10 550 UNITS mA
STANDBY CURRENT: Power-Down Mode; All banks idle, CKE = LOW
ICC2
12
12
12
mA
STANDBY CURRENT: Active Mode; CKE = HIGH, CS\ = HIGH, All banks active after tRCD met; No accesses in progress
ICC3
200
200
200
mA
OPERATING CURRENT: Burst Mode; Page Burst; READ or WRITE, All banks Active
ICC4
675
625
575
mA
AUTO REFRESH CURRENT: tRFC = tRFC MIN CS\ = HIGH, CKE = HIGH
ICC
1350
1250
1150
mA
AUTO REFRESH CURRENT: tRFC = 7.81us CS\ = HIGH, CKE = HIGH
ICC6
20
20
20
mA
SELF REFRESH CURRENT: CKE ICC7
7.5
7.5
7.5
mA
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AC Electrical Characteristics
-75 Parameter Access time from CLK Address Hold Address SetUp CLK High Level width CLK Low Level width Clock Cycle Time CKE Hold Time CKE SetUp Time CS\, RAS\, CAS\, WE\, DQM Hold Time CS\, RAS\, CAS\, WE\, DQM SetUp Time Data-In Hold Time Data-In SetUp Time Data Out High Impedance Time Data-Out Low Impedance Time Data-Out Hold Time (under load) Data-Out Hold Time (no load) ACTIVE to PRECHARGE command ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay REFRESH period (8,192 rows) Industrial REFRESH period (8,192 rows) Enhanced REFRESH period (8,192 rows) Extended AUTO REFRESH period PRECHARGE command period ACTIVE bank a to ACTIVE bank b command Transition Time WRITE Recovery Time CL = 3 CL = 2 Symbol tAC tAC tAH tAS tCH tCL tCK tCK tCKH tCKS tCMH tCMS tDH tDS tHZ tHZ tLZ tOH tOHn tRAS tRC tRCD tREF tREF tREF tRFC rRP tRRD tT tWR MIN MAX 5.4 6 MIN -8 MAX 6 6 MIN -10 MAX 7 7 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms ns ns ns ns
CL = 3 CL = 2
1 1.5 2.5 2.5 7.5 10 1 1.5 1 1.5 1 1.5 5.4 6 1 3 1.8 45 70 20
1 1.5 3 3 8 10 1 2 1 2 1 2 6 6 1 3 1.8 50 70 20
1 2 3 3 10 13 1 2 1 2 1 2 7 7 1 3 1.8 50 70 20
CL = 3 CL = 2
120000
120000
120000
64 32 24 66 20 20 0.3 1CLK + 7ns 15 75 68 20 20 0.3 1CLK + 7ns 15 80
64 32 24 70 20 20 0.3 1CLK + 7ns 15 80
64 32 24
1.2
1.2
1.2
Exit SELF REFRESH to ACTIVE command
tXSR
ns ns
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16M x 72, SDR SDRAM, 3.3v Core/ 3.3v IO
Ordering Information
Part Num ber AS4SD16M72PBG-MS AS4SD16M72PBG-ES
Configuration 4 x 4M x 72/80 4 x 4M x 72/80
Technology SDRAM; SDR SDRAM; SDR
Frequency Non-Functional Functional
VCC 3.3 3.3
Tem p MECH. SAMPLES ENG. SAMPLES
AS4SD16M72PBG-75/IT AS4SD16M72PBG-8/IT AS4SD16M72PBG-10/IT AS4SD16M72PBG-75/ET AS4SD16M72PBG-8/ET AS4SD16M72PBG-10/ET AS4SD16M72PBG-75/XT AS4SD16M72PBG-8/XT AS4SD16M72PBG-10/XT
4 x 4M x 72/80 4 x 4M x 72/80 4 x 4M x 72/80 4 x 4M x 72/80 4 x 4M x 72/80 4 x 4M x 72/80 4 x 4M x 72/80 4 x 4M x 72/80 4 x 4M x 72/80
SDRAM; SDR SDRAM; SDR SDRAM; SDR SDRAM; SDR SDRAM; SDR SDRAM; SDR SDRAM; SDR SDRAM; SDR SDRAM; SDR
133MHz 125MHz 100MHz 133MHz 125MHz 100MHz 133MHz 125MHz 100MHz
3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3
0C - 70C 0C - 70C 0C - 70C -40C - 105C -40C - 105C -40C - 105C -40C - 125C -40C - 125C -40C - 125C
SHADED
Consult Factory for Availability
Austin Semiconductor, Inc.
Proprietary Material
ASI Product Marketing

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